The present disclosure relates to high-speed serial interface links, and more particularly to systems and methods for providing behavior models of such links.
HSSI (high-speed serial interface) applications are well known. Such applications include high-speed transceivers and have been adopted for use in chip-to-chip, board-to-board, backplane, box-to-box, and other designs. In general, a HSSI application or HSSI transceiver includes a transmitter portion, a transmission medium, a receiver portion, and associated circuitry that may support transmission and reception of signals (e.g., clock data recovery circuitry). The transmitter and receiver portions, the transmission medium, and associated circuitry may collectively be referred to herein as a link. The transmission portion may provide data to the receiver portion via the transmission medium at a predetermined data rate. As data rates have increased and continue to increase (up to 10 Gb/s and beyond), HSSI transceivers have become and continue to increase in complexity—to preserve or maintain a certain level of signal integrity. For example, it is desirable to minimize or prevent the occurrence of bit errors in the transmission of data through a link. The occurrence of a bit errors may be quantified as a bit-error-ratio (BER). BER may be influenced by several factors most notably random noise that causes random jitter (RJ) several sources of deterministic jitter (DJ)—inter-symbol-interference (ISI) often being the most dominant contributor, as well as other sources such as cross-talk.
ISI may limit the maximum distance and bit rate carrying capacity of a transmission medium (e.g., a backplane). ISI may be caused by channel impairments such as amplitude attenuation and group delay distortion. In order to compensate for ISI, transceivers may be constructed to have a number of pre-emphasis and/or equalization settings. Optimizing these settings to obtain the best transceiver performance is necessary to maximize link performance for any given link or backplane. Doing so, without aid of link simulation tools, can be time consuming and difficult. Several tools exist, but each is beset with limitations.
Hspice (or other spice-like circuit solvers) is a known tool that may be used to simulate link performance. While Hspice may provide highly accurate silicon level link simulations, a disadvantage of using Hspice to perform a link simulation is that the time required for Hspice to perform a single simulation of a link may take hours or days, depending on the extensiveness of various parameters (e.g., pre-emphasis and equalization settings, transmission mediums, signal characteristics) used. This is because Hspice performs electrical circuit analysis (e.g., current and voltage calculations) when rendering simulations of the link. In addition, the time it takes for an experienced engineer to configure a circuit model and simulation setup may also require an unacceptable period of time. Other tools such as board design tools may exist that provide proprietary models. However, known board design tools do not support link simulations, and are limited to board design. One example is device modeling language (DML) model in Cadence Allegro design environment.
Another known tool is StatEye, which uses MATLAB, to support compliance testing of differential backplane channels. StatEye includes parameterized models for transmitter and receiver and channel function but is not able to incorporate silicon device models with any ease. Furthermore, StatEye also inputs spectral information of sorts that may not accurately reflect what is actually driven in the lab such as certain pseudo-random-sequence (PRBS) or fixed-patterns. Therefore, Stateye may not be able to produce simulation results which accurately correlate to results that would be obtained on an actual link.
What is needed is a tool that accurately and quickly simulates link performance of a transceiver operating with any given transmission medium.